US 2015/0032969 A1Published application

Coherency control message flow

AssigneeArm Limited

InventorsIan BRATT, Mladen WILDER, Ole Henrik JAHREN

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Abstract

A coherent memory system includes a plurality of level 1 cache memories 6 connected via interconnect circuitry 18 to a level 2 cache memory 8. Coherency control circuitry 10 manages coherency between lines of data. Evict messages from the level 1 cache memories to the coherency control circuitry 10 are sent via the read address channel AR. Read messages are also sent via the read address channel AR. The read address channel AR is configured such that a read message may not be reordered relative to an evict message. The coherency control circuitry 10 is configured such that a read message will not be processed ahead of an evict message. The level 1 cache memories 6 do not track in-flight evict messages. No acknowledgement of an evict message is sent from the coherency control circuitry 10 back to the level 1 cache memory 6.

Claims14

Dependent claims

Apparatus for processing data comprising:

a plurality of agents each configured to store one or more lines of data;
coherency control circuitry configured to control coherency between said lines of data stored within said plurality of agents;
and
interconnect circuitry configured to provided communication between said plurality of agents and said coherency control circuitry, said interconnect circuitry providing a plurality of communication channels between each one of said plurality of agents and said coherency control circuitry;
wherein
at least one of said plurality of agents is configured:
(i) to send an evict message to said coherency control circuitry when performing an eviction operation for a line of data via a given one of said plurality of communication channels;
and
(ii) to send a read message to said coherency control circuitry when performing a subsequent read operation for said line of data via said given one of said plurality of communication channels;
said interconnect circuitry is configured always to communicate said evict message and said read message to said coherency control circuitry via said given one of said plurality of communication channels such that said evict message is received by said coherency control circuitry before said read message;
and
said coherency control circuitry is configured always to process said evict message ahead of said read message.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/948,658Filed 23 Jul 2013
Published: 29 Jan 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/0855
Multiple simultaneous or quasi-simultaneous cache accessing: overlapped cache accessing, e.g. pipeline
G06F 12/0815
Multiuser, multiprocessor or multiprocessing cache systems: cache consistency protocols
G06F 12/0828
Using directory methods: with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
G06F 12/0831
Cache consistency protocols: using a bus scheme, e.g. with bus monitoring or watching means