Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations

A processor system, comprising:

• a first chip layer and a second chip layer, which are physically conjoined to form a stacked structure,
• the first chip layer including a first cluster of processor cores and a first L2 cache, wherein each processor core in the first cluster of processor cores is physically connected to the first L2 cache;
• and
• the second chip layer including a first L3 cache, which is aligned to the first L2 cache on the first chip layer, wherein the first L3 cache is physically connected to the first L2 cache through vertical connections between the first and second chip layers,
• wherein the first L2 cache and the first L3 cache form a first cache hierarchy that is physically shared by the first cluster of processor cores.

A processor system, comprising:

• a first chip layer and a second chip layer, which are physically conjoined to foun a stacked structure,
• the first chip layer including a plurality of processor cores;
• the second chip layer including a plurality of L2 caches, a plurality of L3 caches, and an on-chip interconnection network,
• wherein each processor core on the first chip layer is physically connected to a corresponding one of the L2 caches on the second chip layer through vertical connections between the first and second chip layers,
• wherein each L3 cache is physically connected to, and shared by, at least two L2 caches on the second chip layer, such that each L3 cache is shared by two processor cores.