Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface
AssigneeMicron Technology, Inc.
InventorsGiulio ALBINI, Emanuele CONFALONIERI
Life of this patent
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Abstract
Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.
Claims21
1-25. (canceled)
An apparatus comprising:
- memory;
- and
- a controller configured to determine a locking state of a block of the memory associated with a first interface based on a locking state of the block of the memory associated with a second interface,
- wherein locking states of the first interface comprise a locked down state, wherein the locked down state of the first interface is based on a write protect logic state, and
- wherein locking states of the second interface comprise a locked down state, wherein the locked down state of the second interface is not based on the write protect logic state.
A method associated with an operative transition from a first interface to a second interface, the method comprising:
- obtaining a signal representative of a first locking state of a block of a memory, the first locking state being associated with the first interface;
- and
- generating a signal representative of a second locking state of the block of the memory based on the first locking state, wherein the second locking state is associated with the second interface,
- wherein locking states of the first interface comprise a locked down state, wherein the locked down state of the first interface is based on a write protect logic state, and
- wherein locking states of the second interface comprise a locked down state, wherein the locked down state of the second interface is not based on the write protect logic state.
An electronic device comprising:
- memory;
- a plurality of interfaces configured to provide selective access to a block of the memory based on a locking state associated with the block of the memory, the plurality of interfaces comprising a first interface and a second interface, wherein the first interface is further responsive to a write protect logic state associated with the block of memory and the second interface is not further responsive to the write protect logic state;
- and
- a controller configured to:
- change, responsive to an operative transition from the first interface to the second interface, the locking state from a locked state of the first interface to a locked down state of the second interface;
- and
- selectively change, responsive to an operative transition from the second interface to the first interface, the locking state from the locked down state of the second interface to the locked state of the first interface based on the write protect logic state,
- wherein locking states of the first interface comprise a locked down state, wherein the locked down state of the first interface is based on the write protect logic state, and
- wherein the locked down state of the second interface is not based on the write protect logic state.
Dependencies are inferred from the claim text.