US 2015/0032926 A1Published application

Storage apparatus, and system and method for executing access operations

AssigneeHuawei Technologies Co., Ltd.

InventorsChanghong Zhao, Qingxue Zhang

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Abstract

Embodiments of the present invention provide a storage apparatus, and a system and a method for executing access operations. The apparatus includes an interleaved bus, N memory groups, and K direct-connect bus groups, where K is less than or equal to N; the interleaved bus includes M master interfaces and S slave interfaces, where M is less than or equal to S, and each master interface among the M master interfaces is configured to receive continuous-addresses access operations; each memory group among the N memory groups includes S memories respectively connected to the S slave interfaces, where the interleaved bus is configured to decode and send the continuous-addresses access operations to at least one memory group among the N memory groups in an interleaved manner; and a first direct-connect bus group among the K direct-connect bus groups receives and sends the discrete-addresses access operations to at least one memory group.

Claims13

Dependent claims

A storage apparatus, comprising an interleaved bus, N memory groups, and K direct-connect bus groups, wherein K is less than or equal to N, and N and K are both integers;

wherein
the interleaved bus comprises M master interfaces and S slave interfaces, wherein each master interface among the M master interfaces is configured to receive continuous-addresses access operations, M is less than or equal to S, and M and S are both integers;
each memory group among the N memory groups comprises S memories respectively connected to the S slave interfaces, wherein addresses of the S memories in each of the memory groups are continuous, a difference between addresses of two storage units of any one memory among the S memories in each of the memory groups is an integral multiple of S, and the interleaved bus is configured to decode the continuous-addresses access operations, and send the continuous-addresses access operations to at least one memory group among the N memory groups;
and
each direct-connect bus group among the K direct-connect bus groups is connected to at least one memory group among the N memory groups, wherein one end of each direct-connect bus in each of the direct-connect bus groups is used to receive discrete-addresses access operations, the other end of each direct-connect bus is connected to a respective corresponding memory in the at least one memory group, memory groups connected to different direct-connect bus groups are different, and each direct-connect bus group among the K direct-connect bus groups is configured to send the discrete-addresses access operations to at least one memory group among the N memory groups.

2 more elements

A system for executing access operations, comprising a storage apparatus, a first master device, and a second master device, wherein

the storage apparatus comprises an interleaved bus, N memory groups, and K direct-connect bus groups, wherein K is less than or equal to N, and N and K are both integers;
the interleaved bus comprises M master interfaces and S slave interfaces, wherein each master interface among the M master interfaces is coupled to the first master device, M is less than or equal to S, and M and S are both integers;
each memory group among the N memory groups comprises S memories respectively connected to the S slave interfaces, wherein addresses of the S memories in each of the memory groups are continuous, and a difference between addresses of two storage units of any one memory among the S memories in each of the memory groups is an integral multiple of S;
and each direct-connect bus group among the K direct-connect bus groups is connected to at least one memory group among the N memory groups, wherein one end of each direct-connect bus in each of the direct-connect bus groups is coupled to the second master device, the other end of each direct-connect bus is connected to a respective corresponding memory in the at least one memory group, and memory groups connected to different direct-connect bus groups are different;
the first master device is configured to send continuous-addresses access operations to the interleaved bus through any one master interface among the M master interfaces of the interleaved bus, wherein the interleaved bus is configured to decode the continuous-addresses access operations, and send the continuous-addresses access operations to at least one memory group among the N memory groups;
and
the second master device is configured to send discrete-addresses access operations to any one direct-connect bus group among the K direct-connect bus groups, wherein the any one direct-connect bus group is configured to send the discrete-addresses access operations to at least one memory group among the N memory groups.

4 more elements

A method for executing access operations, comprising:

receiving, by an interleaved bus, continuous-addresses access operations through any one master interface among M master interfaces, decoding the continuous-addresses access operations, and sending the continuous-addresses access operations to at least one memory group among N memory groups through S slave interfaces, wherein each memory group among the N memory groups comprises S memories respectively connected to the S slave interfaces, addresses of the S memories in each memory group among the N memory groups are continuous, a difference between addresses of two storage units of any one memory among the S memories in each of the memory groups is an integral multiple of S, M is less than or equal to S, and M, S, and N are all integers;
and
receiving, by a first direct-connect bus group, discrete-addresses access operations, and sending the discrete-addresses access operations to at least one memory group among the N memory groups, wherein the first direct-connect bus group is any one direct-connect bus group among the K direct-connect bus groups, each direct-connect bus group among the K direct-connect bus groups is connected to at least one memory group among the N memory groups, memory groups connected to different direct-connect bus groups are different, K is less than or equal to N, and K is an integer.

Dependencies are inferred from the claim text.