Method of manufacturing a spacer for dual gate electronic memory cell and associated electronic memory cell
AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsAnthony DE LUCA, Christelle Charpin-Nicolle
Life of this patent
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Abstract
A method of manufacturing a spacer for an electronic memory including a substrate; a first gate structure; a stack including a plurality of layers whereof at least one of the layers is able to store electric charges, the method including depositing a spacer material layer, at least on the area covered by the stack; ion beam machining the spacer material layer, the ion beam machining being carried out with controlled stopping so as to preserve a residual portion of the thickness of the spacer material layer covering the stack; plasma etching the residual portion of the thickness of the spacer material layer.
Claims11
A method of manufacturing a spacer for an electronic memory, the electronic memory comprising:
- a substrate which extends along a reference plane;
- a first gate structure deposited on the substrate, the first gate structure having at least one lateral flank;
- a stack comprising a plurality of layers whereof at least one of said layers is able to store electric charges, said stack covering at least the at least one lateral flank of the first gate structure and a portion of the substrate;
- said method comprising:
- depositing a spacer material layer at least on an area covered by the stack;
- ion beam machining the spacer material layer, said ion beam machining being carried out with controlled stopping, so as to preserve a residual portion of the thickness of the spacer material layer covering the stack;
- plasma etching the residual portion of the thickness of the spacer material layer.
A method of manufacturing an electronic memory cell comprising:
- a substrate which extends along a reference plane;
- a first gate structure deposited on the substrate, the first gate structure having at least one lateral flank;
- a stack comprising a plurality of layers whereof at least one of said layers is able to store electric charges, said stack covering at least the at least one lateral flank of the first gate structure and a portion of the substrate;
- a second gate structure, insulated from the first gate structure and from the substrate by the stack, the second gate structure being a spacer of the first gate structure;
- said method comprising manufacturing the second gate structure, said manufacturing comprising a method for manufacturing a spacer according
Dependencies are inferred from the claim text.