Vertical channel transistor with self-aligned gate electrode and method for fabricating the same

A method for fabricating vertical channel transistors, comprising:

• forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate;
• forming a gate dielectric layer on both sidewalls of the pillars;
• forming first gate electrodes which cover any one sidewalls of both sidewalls of the pillars;
• and
• forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.

A method for fabricating a semiconductor device, comprising:

• forming hard mask layer patterns over a semiconductor substrate;
• forming bodies by etching the semiconductor substrate using the hard mask layer patterns as an etch barrier;
• forming buried bit lines in the bodies;
• etching the hard mask layer patterns and upper portions of the bodies to form pillars which have laterally opposing both sidewalls;
• forming first gate electrodes on any one sidewalls of both sidewalls of the pillars;
• forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes;
• and
• forming storage nodes which are connected with the pillars.