Method of cmos manufacturing utilizing multi-layer epitaxial hardmask films for improved epi profile
AssigneeTexas Instruments Incorporated
InventorsDeborah Jean RILEY, Seung-Chul SONG
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Abstract
An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.
Claims20
A method of forming an integrated circuit, comprising the steps of:
- forming a first layer of a dual layer hard mask over a gate of a p-channel metal oxide semiconductor (PMOS) transistor, said first layer being halogen-containing silicon nitride formed by a plasma enhanced chemical vapor deposition (PECVD) process with a halogenated silane reagent and ammonia;
- forming a second layer of said dual layer hard mask on said first layer, said second layer being silicon nitride formed by a PECVD process free of a halogenated reagent;
- removing said second layer and said first layer from horizontal surfaces of said integrated circuit by an anisotropic etch, leaving said second layer and said first layer on lateral surfaces of gate offset spacers disposed on lateral surfaces of said gate of said PMOS transistor;
- subsequently removing material from a substrate of said integrated circuit to form source/drain cavities adjacent to said gate of said PMOS transistor;
- subsequently heating said integrated circuit at a temperature of at least 750° C. for at least 30 seconds in a hydrogen containing ambient which includes at least 0.5 percent hydrogen;
- subsequently forming silicon-germanium (SiGe) source/drain regions in said source/drain cavities by an epitaxial process;
- and
- subsequently removing said second layer and said first layer by a wet etch process.
A method of forming an integrated circuit, comprising the steps of:
- forming a first layer of a dual layer hard mask over a gate of a PMOS transistor and a gate of an NMOS transistor, said first layer being halogen-containing silicon nitride formed by a PECVD process with a halogenated silane reagent and ammonia;
- forming a second layer of said dual layer hard mask on said first layer, said second layer being silicon nitride formed by a PECVD process free of a halogenated reagent;
- forming an etch mask over said second layer of said dual layer hard mask so as to cover said NMOS transistor and expose said PMOS transistor;
- removing said second layer and said first layer from horizontal surfaces of said integrated circuit in areas exposed by said etch mask by an anisotropic etch, leaving said second layer and said first layer on lateral surfaces of gate offset spacers disposed on lateral surfaces of said gate of said PMOS transistor, and leaving said second layer and said first layer over said NMOS transistor;
- subsequently removing said etch mask;
- subsequently removing material from a substrate of said integrated circuit to form source/drain cavities adjacent to said gate of said PMOS transistor;
- subsequently heating said integrated circuit at a temperature of at least 750° C. for at least 30 seconds in a hydrogen containing ambient which includes at least 0.5 percent hydrogen;
- subsequently forming SiGe source/drain regions in said source/drain cavities by an epitaxial process;
- and
- subsequently removing said second layer and said first layer by a wet etch process.
Dependencies are inferred from the claim text.