Semiconductor Device Containing HEMT and MISFET and Method of Forming the Same

A method comprising:

• forming a stack of semiconductor layers over a substrate, each semiconductor layer in the stack of semiconductor layers having a different band gap than an adjacent semiconductor layer in the stack of semiconductor layers;
• forming a capping layer over the stack of semiconductor layers, the capping layer including a first source opening, a first drain opening, a second source opening, and a second drain opening;
• simultaneously forming first and second source and drain features in the respective first and second source and drain openings;
• forming a protection layer over the capping layer, the protection layer including a first gate opening and a second gate opening, wherein the first gate opening and the second gate opening extend through the capping layer;
• forming a gate dielectric material in the first gate opening;
• and
• forming a gate electrode layer in the first gate opening and the second gate opening.

A method comprising:

• epitaxially growing a second III-V compound layer over a first III-V compound layer, the second III-V compound layer having a different band gap than the first III-V compound layer;
• epitaxially growing a third III-V compound layer over the second III-V compound layer;
• forming a dielectric layer over the third III-V compound layer, the dielectric layer including a first source opening, a first drain opening, a second source opening, and a second drain opening;
• simultaneously forming first and second source and drain features in the respective first and second source and drain openings;
• forming a protection layer over the dielectric layer, the protection layer including a first gate opening between the first source feature and first drain feature and a second gate opening between the second source feature and the second drain feature;
• forming a gate dielectric layer in the first gate opening;
• and
• simultaneously forming a first gate electrode in the first gate opening and a second gate electrode in the second gate opening, wherein the gate dielectric is interposed between the first gate electrode and the third III-V compound layer, and wherein the second gate electrode contacts the third III-V compound layer.