Receiver circuit

A receiver circuit comprising:

• a first phase adjuster configured to generate a first clock signal;
• a second phase adjuster configured to generate a second clock signal;
• a first determinator configured to perform binary determination on input data in synchronization with the first clock signal;
• a second determinator configured to perform binary determination on the input data in synchronization with the second clock signal;
• a phase detector configured to detect a phase on the basis of determination values of the first determinator and the second determinator;
• a filter configured to filter on the phase detected by the phase detector and thereby output first phase information;
• an adder configured to add a shift amount to the first phase information and thereby output second phase information;
• and
• a corrector configured to generate third phase information for decreasing variation in phase difference of the first clock signal with respect to the second clock signal,
• wherein the first phase adjuster adjusts a phase of the first clock signal on the basis of the second phase information and the third phase information, and
• wherein the second phase adjuster adjusts a phase of the second clock signal on the basis of the first phase information.