Hierarchical packing of syntax elements

A system for executing memory operations on variable length records, the system comprising:

• a processing element including a plurality of processing lanes, wherein the processing element is configured to generate, concurrently, at least first and second sub-streams of data, and wherein the processing element further includes:
• determining circuitry configured to:
• determine a first number of packs among one or more first packs associated with a first processing lane of the plurality of processing lanes;
• associate the first number of packs with a first used field of the first processing lane;
• determine a second number of packs among one or more second packs associated with a second processing lane of the plurality of processing lanes;
• and
• associate the second number of packs with a second used field of the second processing lane.

A method of operation within an integrated circuit device having a plurality of processing lanes, the method comprising:

• generating a first sub-stream of data in a first processing lane of the plurality of processing lanes;
• generating a second sub-stream of data in a second processing lane of the plurality of processing lanes, wherein the first and second sub-streams are of variable lengths;
• selectively outputting at least the first and second sub-streams to a conditional output stream from respective processing lanes such that only the processing lanes having valid data words output data associated with the first and second sub-streams to the conditional output stream;
• and
• writing the conditional output stream to a memory device.

A system for executing memory operations on variable length records, the system comprising a processing element including a plurality of processing lanes configured to generate, concurrently, at least first and second sub-streams of data, wherein the processing element further includes:

• first generating circuitry configured to generate the first sub-stream of data in a first processing lane of the plurality of processing lanes;
• second generating circuitry configured to generate the second sub-stream of data in a second processing lane of the plurality of processing lanes, wherein the first and second sub-streams are of variable lengths;
• and
• circuitry configured to:
• determine whether each of the processing lanes includes one or more valid data words associated with at least the first and second sub-streams;
• and
• selectively output at least the first and second sub-streams to a conditional output stream from respective processing lanes such that only the processing lanes having the one or more valid data words are configured to output data associated with the first and second sub-streams to the conditional output stream.