Voltage control integrated circuit devices

An integrated circuit, comprising:

• a first voltage divider having an input to receive a reference voltage and having an output providing an adjusted reference voltage, wherein the first voltage divider comprises a plurality of first resistors in series between the input and a first supply node, and a plurality of exit points from the plurality of first resistors in series selectively coupled to the output of the first voltage divider;
• an operational amplifier having a first input coupled to receive the output of the first voltage divider, a second input coupled to receive a feedback voltage, and an output;
• a voltage generation circuit responsive to the output of the operational amplifier and having an output providing an output voltage;
• and
• a second voltage divider having a plurality of entry points selectively coupled to the output of the voltage generation circuit, and an output providing the feedback voltage, wherein the second voltage divider comprises a plurality of second resistors in series between a second supply node and the output of the voltage generation circuit;
• wherein the first voltage divider is responsive to first control signals to adjust a voltage level of the adjusted reference voltage;
• and
• wherein the second voltage divider is responsive to second control signals to adjust a voltage level of the feedback voltage.

An integrated circuit device, comprising:

• an array of memory cells;
• a voltage control circuit to provide voltages to the array of memory cells, wherein the voltage control circuit comprises:
• a first voltage divider coupled to receive a reference voltage and having an output providing an adjusted reference voltage;
• an operational amplifier having a first input coupled to receive the output of the first voltage divider, a second input coupled to receive a feedback voltage, and an output;
• a voltage generation circuit responsive to the output of the operational amplifier and having an output providing an output voltage to the array of memory cells;
• a second voltage divider coupled to receive the output voltage and having an output providing the feedback voltage;
• and
• a decoder to provide first control signals to the first voltage divider to adjust a voltage level of the adjusted reference voltage, and to provide second control signals to the second voltage divider to adjust a voltage level of the feedback voltage.