Device and method for memory repair using test logic

A method for repairing a memory device using a test-bypass register associated with the memory device, the method comprising:

• comparing a current address of the memory device with a faulty address and generating a match signal when the current address matches the faulty address, wherein the faulty address is associated with a non-operational cell of the memory device;
• generating at least one output signal in response to the match signal;
• coupling the at least one output signal to one or more memory-bypass inputs of the test-bypass register;
• and
• configuring the at least one output signal to enable use of the test-bypass register instead of the non-operational cell of the memory device.

A system comprising:

• memory;
• and
• one or more processors coupled to the memory and configured to execute one or more program modules stored in memory to repair a memory device using a test-bypass register associated with the memory device by performing following operations:
• comparing a current address of the memory device with a faulty address and generating a match signal when the current address matches the faulty address, wherein the faulty address is associated with a non-operational cell of the memory device;
• generating at least one output signal in response to the match signal;
• applying the at least one output signal to one or more memory-bypass inputs of the test-bypass register;
• and
• configuring the at least one output signal to enable use of the test-bypass register instead of the non-operational cell of the memory device.