Memory macro with a voltage keeper
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsDEREK C. TAO, BING WANG, ALLEN FAN, YUKIT TANG, ANNIE-LI-KEOW LUM, KUOYUAN HSU
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Abstract
A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line.
Claims20
In a memory macro comprising a memory array, a plurality of first data lines associated with memory cells of the memory array, and a second data line associated with the memory array, a circuit comprising:
- a node coupled with the second data line;
- and
- a first switch comprising a first terminal coupled to the node, and a second terminal coupled to a first one of the first data lines,
- wherein the first switch is configured to electrically couple the second data line via the node to the first one of the first data lines when a memory cell associated with the first one of the first data lines is accessed.
In a memory macro comprising a memory array, a plurality of first data lines associated with memory cells of the memory array, and a second data line associated with the memory array, a circuit comprising:
- a switching device comprising a node coupled to the second data line;
- and
- a control device connected to the switching device, the control device comprising a terminal configured to receive a control signal,
- wherein the control signal is configured to affect a voltage level at the node.
A memory macro comprising:
- a data line;
- a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node;
- and
- a second interface circuit comprising a second node coupled with the data line,
- wherein the voltage keeper is configured to control a voltage level at the second node via the data line.
Dependencies are inferred from the claim text.