Memory device, memory system, and method of controlling read voltage of the memory device

A memory device, comprising:

• a memory cell array comprising a plurality of bit lines and word lines, and a plurality of memory cells located at intersections of the bit lines and word lines, each of the memory cells programmable between at least 2 threshold states;
• a read voltage generator configured to apply a read voltage to selected word lines of the memory cell array;
• a page buffer unit comprising a plurality of page buffers respectively connected to the bit lines of the memory cell array;
• a counter;
• and
• a logic circuit configured to execute a minimal error search (MES) operation, the MES operation including controlling the read voltage generator to sequentially apply different read voltages to the selected word lines, controlling the page buffers to perform logic operations on respective read results corresponding to at least two of the sequentially applied different read voltages, and controlling the counter to count results of the logic operations,
• wherein the different read voltages are in a vicinity between adjacent threshold voltages of adjacent threshold states, and wherein the count results are indicative of a read voltage resulting in a minimal read error between the adjacent threshold states.

A memory system comprising a memory device and a memory controller for controlling the memory device, wherein the memory device comprises:

• a memory cell array comprising a plurality of memory cells;
• a page buffer unit comprising a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively;
• and
• a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation.

A memory system comprising a memory device and a memory controller for controlling the memory device, wherein the memory device comprises:

• a memory cell array comprising a plurality of memory cells;
• a page buffer unit comprising a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively;
• a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation:
• and
• a read voltage generating unit configured to determine a voltage level as a read voltage which corresponds to a valley between two adjacent states of the memory cells based on the number of the counted memory cells, and providing the read voltage to the memory cell array.

A method of controlling a read voltage of a memory device, the memory device configured to operate under control of a memory controller, the method comprising:

• sequentially reading, in the memory device, a plurality of pieces of data from some of a plurality of memory cells of the memory device at different voltage levels;
• performing, in the memory device, a logic operation on the plurality of pieces of data;
• counting, in the memory device, the number of memory cells that exist in each of a plurality of sections defined by the different voltage levels, based on results of the logic operation;
• and
• determining, in the memory device, an optimal voltage level of a read voltage between two adjacent states of the memory cells, based on the number of the counted memory cells.