Wide range multiport bitcell
AssigneeQUALCOMM Incorporated
InventorsChangho Jung, Rakesh Vattikonda, Nishith Desai, Sei Seung Yoon
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Abstract
A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.
Claims20
A circuit for a memory cell, comprising:
- a pair of cross-coupled inverters, wherein a first inverter in the pair is configured to drive a first node for the memory cell and a remaining second inverter in the pair is configured to drive a second node for the memory cell;
- a plurality of read ports configured to access the second node;
- a first write port including a write word line, a complement write word line, and a write bit line;
- a first transmission gate configured to couple the first node to the write bit line responsive to an assertion of the write word line and the complement write word line;
- and
- a power switch configured to isolate the first inverter from a power supply responsive to the assertion of the write word line,
The circuit of claim I, wherein each read port includes a read word line, a read bit line, and a pair of read access transistors coupled to the read word line and the read bit line.
A method of writing to a dual write port memory, comprising
- during a first half of a first write clock cycle, writing to a first bitcell by coupling a write bit line through a first transmission gate to a first node in the first bitcell while isolating a first cross-coupled inverter in the first bitcell from driving the first bitcell's first node;
- and
- during a second half of the first write clock cycle, writing to a second bitcell by coupling the write bit line through a second transmission gate to a first node for the second bitcell while isolating a first cross-coupled inverter in the second bitcell from driving the second bitcell's first node.
A static random access memory (SRAM) cell, comprising:
- a pair of cross-coupled inverters, wherein a first cross-coupled inverter in the pair is configured to drive a first node for the SRAM cell and a remaining second cross-coupled inverter in the pair is configured to drive a second node for the SRAM cell;
- a plurality of read ports configured to access the second node;
- a first write port including a write word line, a complement write word line, and a write bit line;
- a first transmission gate configured to couple the first node to the write bit line responsive to an assertion of the write word line and the complement write word line;
- and
- means for isolating the first cross-coupled inverter from a power supply responsive to the assertion of the write word line and for isolating the first inverter from ground responsive to the assertion of the complement write word line.
Dependencies are inferred from the claim text.