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US 2015/0029778 A1Published application
Mask-programmed read only memory with enhanced security
AssigneeQUALCOMM Incorporated
InventorsSei Seung Yoon, Chulmin Jung, Esin Terzioglu, Steven Millendorf
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Abstract
A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word liens. Each memory cell includes a high Vt transistor and a low Vt transistor.
Claims20
A mask-programmed ROM (MROM) comprising:
- a column line pair including a bit line and a complement bit line;
- and
- a plurality of memory cells, wherein each memory cell includes a pair of transistors comprising a first transistor coupled to the bit line and a second transistor coupled to the complement bit line, and wherein for each pair of transistors, one of the first and second transistors is a low threshold voltage (low Vt) transistor and a remaining one of the first and second transistors is a high threshold voltage (high Vt) transistor.
A method, comprising
- precharging a pair of column lines including a bit line and a complementary bit line;
- asserting a word line to access a memory cell including a first transistor coupled to the hit line and a second transistor coupled to the complementary bit line, wherein one of the first and second transistors is a low Vt transistor and wherein a remaining one of the first and second transistors is a high Vt transistor;
- and
- responsive to the word line assertion, sensing a voltage difference across the precharged pair of column lines to determine which one of the first and second transistors is the low Vt transistor and which one of the first and second transistors is the high Vt transistor to sense a binary value stored in the accessed memory cell.
1 more element
A mask-programmed ROM (MROM) comprising:
- a column line pair including a bit line and a complement bit line;
- a plurality of memory cells, wherein each memory cell includes a pair of transistors comprising a first transistor coupled to the bit line and a second transistor coupled to the complement bit line, and wherein for each pair of transistors, one of the first and second transistors is a low threshold voltage (low Vt) transistor and a remaining one of the first and second transistors is a high threshold voltage (high Vt) transistor;
- and
- means for determining which of the first and second transistors is a high Vt transistor or a low Vt transistor in an accessed one of the memory cells.
1 more element
Dependencies are inferred from the claim text.