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US 2015/0029776 A1Published application
Semiconductor device having a reduced area and enhanced yield
AssigneeMicron Technology, Inc.
InventorHiroki Fujisawa
Life of this patent
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Abstract
A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other.
Claims15
A device comprising:
- a first power supply line supplying a first voltage;
- first, second, and third nodes;
- a selection circuit connected between the first power supply line and the first node;
- a first anti-fuse connected between the first node and the second node;
- and
- a second anti-fuse connected between the first node and the third node, the second and third nodes being not connected to each other.
3 more elements
A device comprising:
- first and second anti-fuses configured to store one bit information, and
- one ends of the first and second anti-fuses being connected to each other to be biased in a same voltage as each other when one of the first and second anti-fuses is programmed, and other ends of the first and second anti-fuses being free from being connected to each other to be biased in a different voltage from each other when the one of the first and second anti-fuses is programmed.
A method comprising:
- performing a programming operation on first and second anti-fuses configured to store one bit information, the performing comprising:
- performing a first connection by applying a first voltage in common to one ends of the first and second anti-fuses, applying a second voltage to other end of the first anti-fuse, and applying a third voltage to other end of the second anti-fuse concurrently, the third voltage being lower than the first voltage and higher than the second voltage;
- and
- performing a second connection by applying the first voltage in common to the one ends of the first and second anti-fuses, applying the third voltage to the other end of the first anti-fuse, and applying the second voltage to the other end of the second anti-fuse concurrently.
1 more element
Dependencies are inferred from the claim text.