Shift register, gate driving unit and display device

A shift register unit comprising a scanning sequence control circuit, a first control circuit and a second control circuit, wherein:

• the scanning sequence control circuit is connected to a first scanning sequence control signal input terminal, a second scanning sequence control signal input terminal, a first clock signal input terminal, a second clock signal input terminal, a set signal input terminal, a reset signal input terminal, a first gate signal output terminal, a second gate signal output terminal, a carry signal output terminal, and a reset signal output terminal, respectively, and the scanning sequence control circuit is configured to control output sequence of a first gate signal and a second gate signal according to the received first scanning sequence control signal and second scanning sequence control signal;
• the first control circuit is configured to output and reset the first gate signal according to the control signals input from the scanning sequence control circuit, and the first control circuit is connected to a frame reset signal input terminal, a power supply voltage input terminal, the first gate signal output terminal and the scanning sequence control circuit, respectively;
• the second control circuit is configured to output and reset the second gate signal according to the control signals input from the scanning sequence control circuit, and the second control circuit is connected to the frame reset signal input terminal, the power supply voltage input terminal, the second gate signal output terminal and the scanning sequence control circuit, respectively.

A gate driving unit, comprising a plurality of shift register units which are connected in cascade:

• a set signal input terminal of each of remaining stages of the shift registers is connected to a carry signal output terminal of a previous stage of the shift register, except that a set signal input terminal of the first stage of the shift register is connected to a clock generating unit;
• a reset signal input terminal of each of remaining stages of the shift registers is connected to a reset signal output terminal of a next stage of the shift register, except that a reset signal input terminal of the last stage of the shift register is connected to the clock generating unit,
• wherein the shift register unit comprises a scanning sequence control circuit, a first control circuit and a second control circuit, wherein:
• the scanning sequence control circuit is connected to a first scanning sequence control signal input terminal, a second scanning sequence control signal input terminal, a first clock signal input terminal, a second clock signal input terminal, a set signal input terminal, a reset signal input terminal, a first gate signal output terminal, a second gate signal output terminal, a carry signal output terminal, and a reset signal output terminal, respectively, and the scanning sequence control circuit is configured to control output sequence of a first gate signal and a second gate signal according to the received first scanning sequence control signal and second scanning sequence control signal;
• the first control circuit is configured to output and reset the first gate signal according to the control signals input from the scanning sequence control circuit, and the first control circuit is connected to a frame reset signal input terminal, a power supply voltage input terminal, the first gate signal output terminal and the scanning sequence control circuit, respectively;
• the second control circuit is configured to output and reset the second gate signal according to the control signals input from the scanning sequence control circuit, and the second control circuit is connected to the frame reset signal input terminal, the power supply voltage input terminal, the second gate signal output terminal and the scanning sequence control circuit, respectively.

A display device, comprising a gate driving unit;

• the display device further comprising:
• a timing controller, configured to generate a stage scanning sequence control signal;
• a voltage generating unit, configured to generate a gate on voltage and a gate off voltage;
• a clock generating unit, configured to generate a first scanning sequence control signal and a second scanning sequence control signal based on the stage scanning sequence control signal, the gate on voltage and the gate off voltage,
• wherein the gate driving unit comprises a plurality of shift register units which are connected in cascade;
• a set signal input terminal of each of remaining stages of the shift registers is connected to a carry signal output terminal of a previous stage of the shift register, except that a set signal input terminal of the first stage of the shift register is connected to a clock generating unit;
• a reset signal input terminal of each of remaining stages of the shift registers is connected to a reset signal output terminal of a next stage of the shift register, except that a reset signal input terminal of the last stage of the shift register is connected to the clock generating unit,
• wherein the shift register unit comprises a scanning sequence control circuit, a first control circuit and a second control circuit, wherein:
• the scanning sequence control circuit is connected to a first scanning sequence control signal input terminal, a second scanning sequence control signal input terminal, a first clock signal input terminal, a second clock signal input terminal, a set signal input terminal, a reset signal input terminal, a first gate signal output terminal, a second gate signal output terminal, a carry signal output terminal, and a reset signal output terminal, respectively, and the scanning sequence control circuit is configured to control output sequence of a first gate signal and a second gate signal according to the received first scanning sequence control signal and second scanning sequence control signal;
• the first control circuit is configured to output and reset the first gate signal according to the control signals input from the scanning sequence control circuit, and the first control circuit is connected to a frame reset signal input terminal, a power supply voltage input terminal, the first gate signal output terminal and the scanning sequence control circuit, respectively;
• the second control circuit is configured to output and reset the second gate signal according to the control signals input from the scanning sequence control circuit, and the second control circuit is connected to the frame reset signal input terminal, the power supply voltage input terminal, the second gate signal output terminal and the scanning sequence control circuit, respectively.