Voltage regulation method and corresponding hpm, chip, and chip system

A hardware performance monitor, at least comprising a first delay circuit and a second delay circuit, wherein:

• the first delay circuit comprises at least one first delay unit of a first threshold voltage Vt type and a first encoding unit;
• wherein:
• an output terminal and an input terminal of the at least one first delay unit are head-to-tail connected to form a loop;
• and the first encoding unit performs encoding according to an output value of the at least one first delay unit, to acquire a first actual output value that can reflect a delay situation of the at least one first delay unit and further reflecting current performance information of the first Vt type;
• the second delay circuit comprises at least one second delay unit of a second Vt type and a second encoding unit;
• wherein:
• an output terminal and an input terminal of the at least one second delay unit are head-to-tail connected to form a loop;
• and the second encoding unit performs encoding according to an output value of the at least one second delay unit, to acquire a second actual output value that can reflect a delay situation of the at least one second delay unit and further reflecting current performance information of the second Vt type;
• and
• the first Vt type and the second Vt type are Vt types that change at different speeds with temperature.

A chip, comprising:

• an adaptive voltage scaling AVS module and at least one hardware performance monitor HPM;
• wherein:
• the AVS module is coupled to the at least one HPM;
• the AVS module comprises an outputting unit, a fitting unit, and a regulating unit, wherein the outputting unit is configured to output a clock signal to the HPM;
• the HPM at least comprises:
• a generating module, a first delay circuit, and a second delay circuit;
• wherein:
• the generating module is configured to generate a corresponding pulse signal according to the clock signal;
• the first delay circuit is configured to perform, for the pulse signal, first delaying related to a first threshold voltage Vt type that is in the chip and changes fastest with temperature, to acquire a first actual output value that can reflect current performance information of the first Vt type;
• the second delay circuit is configured to perform, for the pulse signal, second delaying related to a second Vt type that is in the chip and changes slowest with temperature, to acquire a second actual output value that can reflect current performance information of the second Vt type;
• and the HPM outputs the first and second actual output values to the fitting unit of the AVS module;
• the fitting unit of the AVS module is configured to fit the first and second actual output values at least according to weights of the first and second actual output values to acquire a fitting output value that can reflect current performance information of critical paths in the chip;
• and
• the regulating unit is configured to determine, by comparing the fitting output value with a predetermined reference value, whether to regulate a working voltage of the chip, wherein the predetermined reference value is a fitting output value of the HPM when the chip works with a minimum working voltage at any temperature.

A chip system, wherein the chip system comprises a chip and a power chip;

• wherein the chip comprising:
• an adaptive voltage scaling AVS module and at least one hardware performance monitor HPM;
• wherein:
• the AVS module is coupled to the at least one HPM;
• the AVS module comprises an outputting unit, a fitting unit, and a regulating unit, wherein the outputting unit is configured to output a clock signal to the HPM;
• the HPM at least comprises:
• a generating module, a first delay circuit, and a second delay circuit;
• wherein:
• the generating module is configured to generate a corresponding pulse signal according to the clock signal;
• the first delay circuit is configured to perform, for the pulse signal, first delaying related to a first threshold voltage Vt type that is in the chip and changes fastest with temperature, to acquire a first actual output value that can reflect current performance information of the first Vt type;
• the second delay circuit is configured to perform, for the pulse signal, second delaying related to a second Vt type that is in the chip and changes slowest with temperature, to acquire a second actual output value that can reflect current performance information of the second Vt type;
• and the HPM outputs the first and second actual output values to the fitting unit of the AVS module;
• the fitting unit of the AVS module is configured to fit the first and second actual output values at least according to weights of the first and second actual output values to acquire a fitting output value that can reflect current performance information of critical paths in the chip;
• and the regulating unit is configured to determine, by comparing the fitting output value with a predetermined reference value, whether to regulate a working voltage of the chip, wherein the predetermined reference value is a fitting output value of the HPM when the chip works with a minimum working voltage at any temperature;
• wherein the power chip is configured to supply power for the chip, and when it is determined that a working voltage of the chip needs to be increased, an AVS module of the chip instructs the power chip to input to the chip a working voltage that is a predetermined value higher than an original working voltage;
• and when it is determined that the working voltage of the chip needs to be decreased, the AVS module of the chip instructs the power chip to input to the chip a working voltage that is a predetermined value lower than the original working voltage.