Dcdc converter
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorKei Takahashi
Life of this patent
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Abstract
To provide a DCDC converter achieving low power consumption. A clock generation circuit, an error amplifier, a comparator, and a timer are included in a control circuit. The clock generation circuit, the error amplifier, and the comparator each include a bias circuit and a potential hold portion for intermittently holding a constant potential generated in the bias circuit. The potential hold portion includes a capacitor and a switch. The on or off of the switch is intermittently controlled using the timer. Even in a period in which the supply of voltage is stopped, a signal based on a constant potential generated in the bias circuit is continuously output.
Claims17
A DCDC converter comprising:
- a clock generation circuit configured to output a triangle wave;
- an error amplifier configured to output an error signal;
- a comparator configured to output a control signal in accordance with the triangle wave and the error signal;
- and
- a timer configured to output a switching signal,
- wherein each of the clock generation circuit, the error amplifier, and the comparator comprises:
- a bias circuit configured to output a bias voltage;
- and
- a switch and a capacitor,
- wherein the capacitor is configured to hold the bias voltage intermittently in accordance with the switching signal supplied to the switch.
A DCDC converter comprising:
- a clock generation circuit configured to output a triangle wave;
- an error amplifier configured to output an error signal;
- a comparator configured to output a control signal in accordance with the triangle wave and the error signal;
- and
- a timer configured to output a switching signal,
- wherein each of the clock generation circuit, the error amplifier, and the comparator comprises:
- a bias circuit configured to output a bias voltage;
- and
- a transistor and a capacitor,
- wherein the capacitor is configured to hold the bias voltage intermittently in accordance with the switching signal supplied to the transistor, and
- wherein a channel formation region of the transistor comprises an oxide semiconductor layer.
Dependencies are inferred from the claim text.