US 2015/0028482 A1 · DEVICE LAYOUT FOR REDUCING THROUGH-SILICON-VIA STRESS

Abstract

Approaches for reducing through-silicon via (TSV) stress are provided. Specifically, provided is a device comprising a substrate and a TSV formed in the substrate, the TSV having an element patterned therein. The TSV further comprises a set of openings adjacent the element that are subsequently filled with a TSV fill material. The element may be patterned according to any number of shapes (e.g., circle, oval, rectangle, etc.) to optimize the stress distribution for the TSV. The element is patterned and provided within the TSV in order to reduce or compensate for stress forces caused by a change in volume of the conductive fill materials of the openings of the TSV. These approaches apply to both single TSVs and a plurality of TSVs (e.g., arranged as a matrix).

Claims20

Dependent claims

A device comprising:

a substrate;
and
a plurality of through-silicon-vias (TSVs) formed in the substrate, the plurality of TSVs each having a substantially vertical element patterned therein, wherein the plurality of TSVs are arranged in a matrix configuration, and wherein a set of TSVs from the plurality of TSVs positioned closer to a center of the matrix are larger in size than another set of TSVs from the plurality of TSVs positioned further away from the center of the matrix.

Dependencies are inferred from the claim text.

Device layout for reducing through-silicon-via stress

Life of this patent

Device layout for reducing through-silicon-via stress

Life of this patent

Abstract

Claims20