Stack packages and methods of fabricating the same
AssigneeSK hynix Inc.
InventorsJong Hoon KIM, Han Jun BAE
Life of this patent
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Abstract
Stack packages are provided. The stack package includes a first chip and a second chip. The first chip includes a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body. The second chip includes a second chip body and bumps disposed on a top surface of the second chip body. The first and second chips are vertically stacked such that the bumps penetrate the insulation layer to pierce the first through electrodes and the top surface of the second chip body directly contacts the insulation layer. Related fabrication methods, electronic systems and memory cards are also provided.
Claims20
A stack package comprising:
- a first chip configured to include a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body;
- and
- a second chip configured to include a second chip body and bumps disposed on a top surface of the second chip body,
- wherein the first and second chips are vertically stacked such that the bumps of the second chip penetrate the insulation layer of the first chip to pierce the first through electrodes of the first chip.
A method of fabricating a stack package, the method comprising:
- providing a plurality of chips, each of the chips including a chip body, through electrodes penetrating the chip body, an insulation layer disposed on a bottom surface of the chip body, and bumps disposed on a top surface of the chip body;
- vertically aligning the chips with each other;
- and
- heating and pressurizing the aligned chips such that the bumps of an upper chip of the chips penetrate the insulation layer of a lower chip of the chips to pierce the through electrodes of the lower chip.
Dependencies are inferred from the claim text.