Stacked package and method for manufacturing the same
AssigneeSK hynix Inc.
InventorYoung Berm JUNG
Life of this patent
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Abstract
The stacked package includes: a substrate having an upper surface formed with connection pads, a lower surface, and four side surfaces; a first semiconductor chip mounted over the upper surface of the substrate; a first adhesive member that covers a portion of the substrate including the first semiconductor chip; and a second semiconductor chip formed with bumps on edges of a first surface and mounted over the substrate with interposition of the first semiconductor chip and the first adhesive member such that a center of the first surface is attached over the first adhesive member and the bumps are bonded onto the connection pads, with a second surface opposing to the first surface being polished evenly.
Claims20
A stacked package, comprising:
- a substrate having an upper surface formed with connection pads, a lower surface, and four side surfaces;
- a first semiconductor chip mounted over the upper surface of the substrate;
- a first adhesive member that covers a portion of the upper surface of the substrate including the first semiconductor chip;
- and
- a second semiconductor chip formed with bumps on edges of a first surface and mounted over the substrate by interposing the first semiconductor chip and the first adhesive member such that a center of the first surface is attached over the first adhesive member and the bumps are bonded to the connection pads, with a second surface opposing to the first surface being polished evenly.
A method for manufacturing a stacked package, comprising the steps of:
- mounting a first semiconductor chip over a upper surface of a substrate having the upper surface formed with connection pads, a lower surface, and four side surfaces that couple the upper surface and the lower surface;
- forming a first adhesive member over the upper surface of the substrate to cover a portion of the upper surface of the substrate including the first semiconductor chip;
- mounting over the upper surface of the substrate a second semiconductor chip formed with bumps on edges of a first surface such that a center of the first surface is attached over the first adhesive member and the bumps are bonded to the connection pads of the substrate;
- and
- planarizing a second surface of the second semiconductor chip opposite to the first surface by polishing the second surface.
Dependencies are inferred from the claim text.