Through-Silicon Coaxial Via Structure And Method
AssigneeAvago Technologies General IP (Singapore) Pte.Ltd.
InventorsAdam E. Gallegos, Thomas E. Cynkar
Life of this patent
Estimating the term…
Abstract
A silicon interconnect structure includes a peripheral outer via in a silicon substrate, a solid core inner via in the silicon substrate, the solid core inner via coaxial with the peripheral outer via to form a coaxial via structure, a metal interconnect stack formed over a first surface of the peripheral outer via and the solid core inner via, at least portions of the metal interconnect stack forming an electrical connection with the peripheral outer via and the solid core inner via, first contact pads on a surface of the metal interconnect stack, and second contact pads on an exposed surface of the peripheral outer via and the solid core inner via.
Claims20
A silicon interconnect structure, comprising:
- a peripheral outer via in a silicon substrate;
- a solid core inner via in the silicon substrate, the solid core inner via coaxial with the peripheral outer via to form a coaxial via structure;
- a metal interconnect stack formed over a first surface of the peripheral outer via and the solid core inner via, at least portions of the metal interconnect stack forming an electrical connection with the peripheral outer via and the solid core inner via;
- first contact pads on a surface of the metal interconnect stack;
- and
- second contact pads on an exposed surface of the peripheral outer via and the solid core inner via.
A method of making a silicon interconnect structure, comprising:
- forming an opening in a silicon substrate;
- forming a first insulator over at least portions of the silicon substrate;
- forming a first conductor over at least portions of the first insulator;
- forming a second insulator over at least portions of the first conductor;
- forming a second conductor over at least portions of the second insulator;
- planarizing a first surface of the second conductor to expose the first conductor and the second conductor;
- forming a metal interconnect stack over the first surface;
- back grinding a second surface of the silicon substrate to expose the first conductor and the second conductor;
- forming a third insulator on the second surface to form openings for electrical contacts on the second surface;
- forming a third conductor on the second surface, the third conductor in electrical connection with the first conductor;
- and
- applying solder bumps to the electrical contacts on the second surface.
An integrated circuit package, comprising:
- a package substrate;
- a silicon interposer structure located over the package substrate, the silicon interposer structure comprising:
- a peripheral outer via in a silicon substrate;
- a solid core inner via in the silicon substrate, the solid core inner via coaxial with the peripheral outer via to form a coaxial via structure;
- a metal interconnect stack formed over a first surface of the peripheral outer via and the solid core inner via, at least portions of the metal interconnect stack forming an electrical connection with the peripheral outer via and the solid core inner via;
- first contact pads on a surface of the metal interconnect stack;
- and
- second contact pads on an exposed surface of the peripheral outer via and the solid core inner via.
Dependencies are inferred from the claim text.