Mol insitu pt rework sequence
AssigneeGlobalfoundries Inc.
InventorsPeter BAARS, Marco LEPPER, Uwe KAHLER, Vivien SCHROEDER
Life of this patent
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Abstract
The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.
Claims20
A device comprising:
- a semiconductor substrate;
- gate electrodes on the semiconductor substrate;
- spacers on each side of each gate electrode;
- and platinum-containing nickel silicide on the substrate adjacent each spacer, wherein the device is at least 99% free from platinum residues.
A device comprising:
- a semiconductor substrate;
- high K metal gate electrodes on the semiconductor substrate;
- spacers on each side of each gate electrode;
- platinum-containing nickel silicide on the substrate adjacent each spacer;
- and
- nitride stress liners on the gate electrodes and on the platinum-containing nickel silicide,
- wherein the device is at least 99% free from platinum residues and wherein the platinum-containing nickel silicide is formed by:
- sputter depositing a layer of nickel (Ni)/platinum (Pt) from a Ni/Pt target on the substrate;
- performing a first rapid thermal anneal (RTA);
- wet stripping unreacted Ni;
- performing a second RTA;
- stripping unreacted Pt from the annealed Ni/Pt layer;
- treating the Pt stripped Ni/Pt layer with an oxygen plasma;
- cleaning the Ni/Pt layer with an SPM/APM clean;
- and
- stripping unreacted Pt from the cleaned Ni/Pt layer.
A device comprising:
- a plurality of semiconductor wafers;
- at least one gate electrode on each semiconductor wafer;
- platinum-containing nickel silicide on opposite sides of each gate electrode;
- spacers separating the platinum-containing nickel silicide and each gate electrode;
- and
- nitride stress liners on the gate electrodes and on the platinum-containing nickel silicide,
- wherein the device is at least 99% free from platinum-containing residues.
Dependencies are inferred from the claim text.