Semiconductor device with reduced defects
AssigneeSemiconductor Manufacturing International Corp.
InventorHUALONG SONG
Life of this patent
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Abstract
A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer.
Claims19
1-9. (canceled)
A semiconductor structure, comprising:
- a conditioned semiconductor substrate, conditioned from a semiconductor substrate having a rough surface, obtained from a chemical mechanical polishing process in removing an oxide layer from the semiconductor substrate, the conditioned semiconductor substrate having a significantly smooth surface from a thermal annealing process to the rough surface using an inert gas consisting of argon, helium, and neon as a thermal annealing protective gas;
- a gate structure formed on the conditioned semiconductor substrate, wherein the gate structure includes:
- an insulating layer disposed on the conditioned semiconductor substrate having the significantly smooth surface, wherein the insulating layer has reduced deformation or defects compared with an insulating layer formed on the semiconductor substrate having the rough surface,
- a high-K gate dielectric layer disposed on the insulating layer,
- a protective layer disposed on the high-K gate dielectric layer, and
- a gate electrode layer disposed on the protective layer;
- sidewalls covering sides of the gate structure;
- and
- source and drain regions formed in the conditioned semiconductor substrate on both adjacent sides of the gate structure.
(canceled)
A transistor device, comprising:
- a conditioned semiconductor substrate, conditioned to enable silicon atoms in a semiconductor substrate to migrate and to fill defects on a surface of the semiconductor substrate to provide a significantly smooth surface by a thermal annealing process using an inert monatomic gas consisting of argon, helium, and neon as a thermal annealing protective gas;
- and
- a gate structure disposed on the conditioned semiconductor substrate, wherein the gate structure includes:
- an insulating layer disposed on the conditioned semiconductor substrate having the significantly smooth surface, wherein the insulating layer has reduced deformation or defects compared with an insulating layer formed on the semiconductor substrate,
- a high-K gate dielectric layer disposed on the insulating layer, wherein the high-K gate dielectric layer has reduced deformation or defects compared with a high-K gate dielectric layer disposed over the semiconductor substrate,
- a protective layer disposed on the high-K gate dielectric layer, and
- a gate electrode layer disposed on the protective layer.
Dependencies are inferred from the claim text.