Thin film transistor, array substrate and manufacturing method thereof, and display panel
AssigneesChengdu Boe Optoelectronics Technology Co., Ltd., Boe Technology Group Co., Ltd.
InventorsWon Seok Kim, Pil Seok Kim
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Abstract
Embodiments of the invention provide a thin film transistor, an array substrate and a manufacturing method thereof, and a display panel. The thin film transistor comprises: an active layer pattern, a source electrode, a drain electrode and a gate electrode. The gate electrode is positioned above the active layer pattern, the source electrode is connected with the active layer pattern, the drain electrode is connected with the active layer pattern, and the source electrode and the drain electrode are disposed in an adjacent layer of the active layer pattern.
Claims14
A thin film transistor, comprising an active layer pattern, a source electrode, a drain electrode and a gate electrode,
- wherein the gate electrode is positioned above the active layer pattern, the source electrode is connected with the active layer pattern, the drain electrode is connected with the active layer pattern, and the source electrode and the drain electrode are disposed in an adjacent layer of the active layer pattern.
An array substrate, wherein the array substrate comprises a base substrate, and gate lines and data lines located above the base substrate, wherein the gate lines and the data lines cross with each other to define a plurality of pixel regions, and a pixel electrode and a thin film transistor is formed in each of the pixel regions,
- the thin film transistor comprises an active layer pattern, a source electrode, a drain electrode and a gate electrode, the gate electrode is positioned above the active layer pattern, the source electrode is respectively connected with the active layer pattern and one of the data lines, the drain electrode is respectively connected with the active layer pattern and the pixel electrode, and the source electrode and the drain electrode are disposed in an adjacent layer of the active layer pattern.
(canceled)
A method of manufacturing an array substrate, wherein the method comprises:
- Step 100, forming an active layer pattern and a pixel electrode on a base substrate;
- Step 102, forming data lines, a source electrode and a drain electrode on the base substrate after the step 100, on end of the source electrode is connected with one of the data lines, the other end of the source electrode is formed on the active layer pattern, one end of the drain electrode is formed on the active layer pattern, and the other end of the drain electrode is formed on the pixel electrode;
- Step 104, forming a first insulation layer on the base substrate after the step 102, wherein the first insulation layer covers the base substrate;
- and
- Step 106, forming gate lines and a gate electrode on the first insulation layer, wherein the gate electrode is connected with one of the gate lines and is located above the active layer pattern.
Dependencies are inferred from the claim text.