3d high voltage charge pump

A charge pump comprising:

• a pump circuit;
• and
• a pump capacitor, wherein the pump capacitor comprises
• a substrate including a capacitor region in which the capacitor is disposed, the capacitor includes
• a first sub-capacitor (C1), the first sub-capacitor comprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate, the gate includes agate electrode over a gate dielectric, wherein
• a first C1 plate is served by the gate electrode,
• a second C1 plate is served by the substrate of the capacitor region, and
• a C1 capacitor dielectric is served by the gate dielectric,
• a second sub-capacitor (C2), the second sub-capacitor comprises a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels, wherein a plurality of metal lines are disposed in the metal levels, the metal lines of a metal level are grouped in alternating first and second groups, the first group serves as first C2 plates and second group serves as second C2 plates and the dielectric layers between the first and second groups serve as C2 capacitor dielectrics;
• a third sub-capacitor (C3), wherein
• a first C3 plate is served by the gate electrode,
• a second C3 plate is served by second group lines in the first metal level of the ILD layers, and
• a C3 capacitor dielectric is formed by the first via level dielectric below M1 and above the gate electrode;
• a first capacitor terminal coupled to first capacitor plates of C1, C2 and C3;
• and
• a second capacitor terminal coupled to second capacitor plates of C1, C2 and C3.

A capacitor comprising:

• a substrate including a capacitor region in which the capacitor is disposed, wherein the capacitor includes
• a first sub-capacitor (C1), the first sub-capacitor comprises a metal oxide semiconductor (MOS) capacitor,
• a second sub-capacitor (C2), the second sub-capacitor comprises a back-end-of line vertical capacitor disposed in interlevel dielectric (ILD) layers with metal levels and via levels over the substrate, and
• a third sub-capacitor (C3), the third sub-capacitor is disposed in between C1 and
• C2, a first C3 plate is served by gate electrode of the MOS capacitor, a second C3 plate is served by one group of metal lines in the lowest metal level of the ILD layers and a C3 capacitor dielectric is formed by a dielectric layer of the ILD layers above the gate electrode.

A method for forming a device comprising:

• providing a substrate having a capacitor region in which a capacitor is formed;
• forming the capacitor having first, second and third sub-capacitors, wherein forming the capacitor comprises
• performing front-end-of-line processes to form the first sub-capacitor (C1) of the capacitor, wherein the first sub-capacitor comprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate, the gate includes a gate electrode over a gate dielectric, wherein
• a first C1 plate is served by the gate electrode,
• a second C1 plate is served by the substrate of the capacitor region, and
• a C1 capacitor dielectric is served by the gate dielectric;
• performing back-end-of-line (BEOL) processes to form the second sub-capacitor (C2) of the capacitor, wherein the second sub-capacitor comprises a vertical capacitor disposed in ILD layers with metal levels and via levels, wherein a plurality of metal lines are disposed in the metal levels, the metal lines of a metal level are grouped in alternating first and second groups, the first group serves as first C2 plates and second group serves as second C2 plates and the dielectric layers between the first and second groups serve as C2 capacitor dielectrics, wherein
• the third sub-capacitor (C3) is formed between C1 and C2, wherein
• a first C3 plate is served by the gate electrode,
• a second C3 plate is formed by second group lines in the first metal level of the ILD layers, and
• a C3 capacitor dielectric is formed by the first via level dielectric below M1 and above the gate electrode;
• coupling the first capacitor plates of C1, C2 and C3 to a first capacitor terminal;
• and
• coupling the second capacitor plates of C1, C2 and C3 to a second capacitor terminal.