Arrays Of Recessed Access Gate Lines, Arrays Of Conductive Lines, Arrays Of Recessed Access Gate Lines And Conductive Lines, Memory Circuitry, Methods Of Forming An Array Of Recessed Access Gate Lines, Methods Of Forming An Array Of Conductive Lines, And Methods Of Forming An Array Of Recessed Access Gate Lines And An Array Of Conductive Lines

An array of recessed access gate lines and conductive lines, comprising:

• active area regions having dielectric trench isolation material there-between, the trench isolation material comprising dielectric end projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions, the active area material being elevationally over the dielectric end projections, the trench isolation material comprising dielectric lateral projections extending laterally into opposing sides proximate the opposing ends under an elevationally outermost surface of the active area material proximate the opposing ends, the active area material being elevationally over the dielectric end projections proximate the opposing ends;
• recessed access gate lines individually extending transversally across the active area regions and extending between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material;
• and
• conductive lines individually extending transversally across and elevationally over a mid-portion of the individual active area regions, conductive material being directly against a mid-portion surface of the active area material of the individual active area regions and being conductively coupled to the conductive line transversally crossing thereover, the mid-portion surface being elevationally inward relative to the elevationally outermost surface of the active area material in the individual active area regions proximate the opposing ends.

An array of recessed access gate lines and conductive lines, comprising:

• active area regions having dielectric trench isolation material there-between, the trench isolation material comprising dielectric end projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions, the active area material being elevationally over the dielectric end projections, the trench isolation material comprising dielectric lateral projections extending laterally into opposing sides proximate the opposing ends under an elevationally outermost surface of the active area material proximate the opposing ends, the active area material being elevationally over the dielectric end projections proximate the opposing ends;
• recessed access gate lines individually extending transversally across the active area regions and extending between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material;
• and
• conductive lines individually extending transversally across and elevationally over a mid-portion of the individual active area regions, conductive material being directly against a mid-portion surface of the active area material of the individual active area regions and being conductively coupled to the conductive line transversally crossing thereover, the individual active area regions being longitudinally elongated along a straight longitudinal axis, the mid-portion surface being laterally narrower perpendicular to the longitudinal axis than the elevationally outermost surfaces proximate the opposing ends.

A method of forming an array of recessed access gate lines, comprising:

• etching isolation trenches into semiconductor material to a first depth to define active area regions;
• etching the isolation trenches deeper into the semiconductor material to a second depth, the etching to the second depth projecting the isolation trenches longitudinally into opposing ends of individual active area regions below the first depth;
• forming dielectric trench isolation material in the extended isolation trenches including projecting portions thereof to form dielectric projections extending into the opposing ends of the individual active area regions under an elevationally outermost surface of the semiconductor material of the active area regions, the semiconductor material being elevationally over the dielectric projections;
• and
• forming recessed access gate lines which individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material.

A method of forming an array of conductive lines, comprising:

• etching isolation trenches into semiconductor material to a first depth to define active area regions;
• etching the isolation trenches deeper into the semiconductor material to a second depth, the etching to the second depth projecting the isolation trenches laterally into opposing sides of individual active area regions below the first depth;
• forming dielectric trench isolation material in the extended isolation trenches including projecting portions thereof to form dielectric projections extending laterally into the opposing sides of the individual active area regions under an elevationally outermost surface of the semiconductor material of the active area regions, the semiconductor material being elevationally over the dielectric projections;
• etching a contact opening into the semiconductor material at a mid-portion of the individual active area regions to form a mid-portion semiconductor material surface that is elevationally inward relative to the elevationally outermost surface of the semiconductor material in the individual active area regions;
• and
• forming conductive lines that individually extend transversally across and elevationally over the mid-portions of the active area regions, conductive material being directly against the mid-portion surface of the individual active area regions and being conductively coupled to the conductive line transversally crossing thereover.

A method of forming an array of recessed access gate lines and an array of conductive lines, comprising:

• etching isolation trenches into semiconductor material to a first depth to define active area regions;
• etching the isolation trenches deeper into the semiconductor material to a second depth, the etching to the second depth projecting the isolation trenches longitudinally into opposing ends of individual active area regions below the first depth and projecting the isolation trenches laterally into opposing sides of the individual active area regions below the first depth;
• forming dielectric trench isolation material in the extended isolation trenches including projecting portions thereof to form dielectric end projections extending into the opposing ends of the individual active area regions under an elevationally outermost surface of the semiconductor material of the active area regions and to form dielectric lateral projections extending laterally into the opposing sides of the individual active area regions under the elevationally outermost surface of the semiconductor material of the active area regions, the semiconductor material being elevationally over the end and lateral dielectric projections;
• forming recessed access gate lines which individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material;
• after forming the recessed access gate lines, etching a contact opening into the semiconductor material at a mid-portion of the individual active area regions to form a mid-portion semiconductor material surface that is elevationally inward relative to the elevationally outermost surface of the semiconductor material in the individual active area regions;
• and
• forming conductive lines that individually extend transversally across and elevationally over the mid-portions of the active area regions, conductive material being directly against the mid-portion surface of the individual active area regions and being conductively coupled to the conductive line transversally crossing thereover.