Semiconductor device with isolation insulating layer containing air gap

A semiconductor device comprising:

• a semiconductor substrate having a main surface;
• a first conductivity type impurity layer located over the main surface of the semiconductor substrate;
• a photoelectric transducer including a first conductivity type impurity region and a second conductivity type impurity region which are joined to each other over the first conductivity type impurity layer;
• and
• a transistor configuring a unit pixel including the photoelectric transducer and being electrically coupled to the photoelectric transducer,
• wherein at least part of an area around the photoelectric transducer in a plan view contains an air gap and has an isolation insulating layer for electrically insulating the one photoelectric transducer and the other photoelectric transducer adjacent to the one photoelectric transducer from each other, and
• wherein the isolation insulating layer abuts on a top surface of the first conductivity type impurity layer,
• wherein a bottom of the air gap is in a position deeper than a bottom of the photoelectric transducer,
• wherein a plurality of the unit pixels are arranged in a matrix pattern,
• wherein the transistor includes a first transistor formed in a first active region including a first impurity region as the photoelectric transducer and a second impurity region as an impurity diffusion layer, and a second transistor, included in the unit pixel, which is electrically coupled to the first transistor and formed in a second active region including an impurity region as an impurity diffusion layer, and
• wherein a shortest distance between the first active region of the first transistor included in one unit pixel of a pair of neighboring unit pixels among the plural unit pixels and the first active region of the first transistor included in the other unit pixel of the pair of unit pixels is smaller than a shortest distance between the first active region of the first transistor and the second active region of the second transistor adjacent to the first transistor in a plan view.