Zram heterochannel memory
AssigneeInternational Business Machines Corporation
InventorsAndres BRYANT, Lyndon R. LOGAN, Edward J. NOWAK, Robert R. ROBISON
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AssigneeInternational Business Machines Corporation
InventorsAndres BRYANT, Lyndon R. LOGAN, Edward J. NOWAK, Robert R. ROBISON
Estimating the term…
Approaches for zero capacitance memory cells are provided. A method of manufacturing a semiconductor structure includes forming a channel region by doping a first material with a first type of impurity. The method includes forming source/drain regions by doping a second material with a second type of impurity different than the first type of impurity, wherein the second material has a smaller bandgap than the first material. The method includes forming lightly doped regions between the channel region and the source/drain regions, wherein the lightly doped regions include the second material. The method includes forming a gate over the channel region, wherein the second material extends under edges of the gate.
A method of manufacturing a semiconductor structure, comprising:
A method of forming a semiconductor structure, comprising:
A semiconductor structure, comprising:
Dependencies are inferred from the claim text.