GaN DEVICE WITH REDUCED OUTPUT CAPACITANCE AND PROCESS FOR MAKING SAME

A transistor device comprising:

• at least one buffer layer disposed on a substrate layer;
• a barrier layer disposed on the at least one buffer layer with a two dimensional electron gas (2DEG) disposed at an interface between the barrier layer and the buffer layer;
• gate electrode disposed on the barrier layer;
• a dielectric layer disposed on the gate electrode and the barrier layer;
• a first isolation region and a second isolation region each formed in respective first and second portions of the interface between the at least one buffer layer and the barrier layer, such that the 2DEG is removed from the first and second portions of the interface where the isolation region is formed.

A method for fabricating a transistor device, the method comprising:

• forming at least one buffer layer on a substrate layer;
• forming a barrier layer on the at least one buffer layer with a two dimensional electron gas (2DEG) disposed at an interface between the barrier layer and the buffer layer;
• forming a gate electrode on the barrier layer;
• and
• forming a first isolation region in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG from the portion of the interface where the isolation region is formed.