III-V Device with Overlapped Extension Regions Using Replacement Gate

A method of forming a semiconductor device, comprising the steps of:

• forming a III-V compound semiconductor-containing heterostructure having at least one layer;
• forming a T-shaped gate structure using a gate replacement process, the T-shaped gate structure having a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the III-V compound semiconductor-containing heterostructure;
• forming gate spacers on the upper surface of the III-V compound semiconductor-containing heterostructure adjacent to and contacting a vertical portion of the T-shaped gate structure, the gate spacers having an outer side that is substantially flush with an outer side of the T-shaped gate structure;
• forming raised source-drain (RSD) regions on the upper surface of the III-V compound semiconductor-containing heterostructure adjacent to and contacting the gate spacers;
• and
• forming dielectric regions on an upper surface of the RSD regions, the dielectric regions contacting the gate spacers and contacting the outer side of the T-shaped gate structure and having an upper surface that is substantially flush with the upper surface of the T-shaped gate structure.

A semiconductor structure, comprising:

• a III-V compound semiconductor-containing heterostructure having at least one layer;
• a T-shaped gate structure having a bottom surface on a channel layer substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the III-V compound semiconductor-containing heterostructure;
• gate spacers on the upper surface of the III-V compound semiconductor-containing heterostructure adjacent to and contacting a vertical portion of the T-shaped gate structure, the gate spacers having an outer side that is substantially flush with an outer side of the T-shaped gate structure;
• and
• raised source-drain (RSD) regions on the upper surface of the III-V compound semiconductor-containing heterostructure adjacent to and contacting the gate spacers.