III-V FET Device with Overlapped Extension Regions Using Gate Last

A method of forming a semiconductor device, comprising the steps of:

• forming a III-V compound semiconductor-containing heterostructure;
• forming a doped contact layer on the III-V compound semiconductor-containing heterostructure;
• forming a dielectric layer on the doped contact layer;
• forming a gate trench extending from an upper surface of the dielectric layer, through the doped contact layer, to a barrier layer that is substantially below an upper surface of the III-V compound semiconductor-containing heterostructure;
• forming gate spacers on sidewalls of the gate trench and on the barrier layer, the gate spacers having an upper surface that is substantially flush with the upper surface of the dielectric layer;
• forming a gate region by removing the barrier layer from the region of the gate trench between the gate spacers;
• and
• forming a gate structure in the gate region, the gate structure having an upper surface that is substantially flush with the upper surface of the gate spacers.

A semiconductor structure, comprising:

• a III-V compound semiconductor-containing heterostructure;
• a doped contact layer on the III-V compound semiconductor-containing heterostructure;
• a dielectric layer on the doped contact layer;
• a gate structure having an upper surface that is substantially flush with an upper surface of the dielectric layer and having a bottom surface on a barrier layer that is substantially below an upper surface of the III-V compound semiconductor-containing heterostructure;
• and
• gate spacers on an upper surface of the barrier layer adjacent to and contacting the gate structure, the gate spacers having an upper surface that is substantially flush with the upper surface of the dielectric layer.