GaN TRANSISTORS WITH POLYSILICON LAYERS FOR CREATING ADDITIONAL COMPONENTS

An integrated circuit comprising:

• a channel layer;
• a barrier layer disposed over the channel layer;
• a source metal and a drain metal disposed on the barrier layer;
• a gate structure disposed between the source and drain metal;
• an insulating material disposed over the source metal, drain metal and gate structure;
• a polysilicon layer disposed in the insulating material, the polysilicon layer having at least one p-type region;
• and
• a plurality of metal interconnects disposed on the insulating material, each metal interconnect connected to at least one of the source metal, the drain metal, and the at least one p-type region of the polysilicon layer by a plurality of vias, respectively.

A method of manufacturing an integrated circuit, the method comprising:

• depositing a channel layer over at least one buffer layer;
• depositing a barrier layer over the channel layer, such that a two dimensional electron gas (2DEG) region is formed at an interface between the channel layer and the barrier layer;
• forming an isolation region in the barrier layer and the channel layer to electrically isolate a first portion of the 2DEG region from a second portion of the 2DEG region;
• forming a gate structure for an enhancement mode device over the first portion of the 2DEG region;
• depositing a first insulating layer over the gate structure;
• forming a back gate over the second portion of the 2DEG region;
• depositing a second insulating layer over the back gate;
• depositing a polysilicon layer on the second insulating layer and etching the polysilicon layer, such that at least a portion of the etched polysilicon layer is disposed over the back gate;
• doping the etched polysilicon layer to form at least one p-type region in the polysilicon layer;
• depositing a third insulating layer on the etched polysilicon layer;
• and
• forming at least one metal interconnect layer on the third insulating layer that is electrically coupled to the at least one p-type region of the polysilicon layer by at least one via formed in the third insulating layer.

An integrated circuit comprising:

• a channel layer disposed over at least one buffer layer;
• a barrier layer disposed over the channel layer, with a two dimensional electron gas (2DEG) region formed at an interface between the channel layer and the barrier layer;
• an isolation region disposed in the barrier layer and the channel layer to electrically isolate a first portion of the 2DEG region from a second portion of the 2DEG region;
• a gate structure for an enhancement mode device disposed over the first portion of the 2DEG region;
• a first insulating layer disposed over the gate structure;
• a back gate disposed over the second portion of the 2DEG region;
• a second insulating layer disposed over the back gate;
• a polysilicon layer disposed on the second insulating layer and over the back gate, the polysilicon layer including at least one p-type region;
• a third insulating layer disposed on the etched polysilicon layer;
• and
• at least one metal interconnect layer disposed on the third insulating layer that is electrically coupled to the at least one p-type region of the polysilicon layer by at least one via formed in the third insulating layer.