Power MOS Transistor with Integrated Gate-Resistor

A gate-resistor structure on a semiconductor body, the semiconductor body comprising a gate electrode of a first conductivity type or a second conductivity type, the gate electrode comprising a top surface, the gate structure comprises:

• a first semiconductor region of the first conductivity type, extending from the top surface into the gate electrode in a vertical direction;
• a second semiconductor region of the second conductivity type, arranged adjacent to the first semiconductor region, thus forming a p-n junction with the first semiconductor region, the second semiconductor region being arranged below the first semiconductor region in a vertical direction;
• an insulating layer arranged to insulate the first semiconductor region from the surrounding gate electrode;
• a contact layer arranged on the top surface, covering the first semiconductor region to electrically connect the first semiconductor region and additionally covering portions of the top surface beside the first semiconductor region in a horizontal direction.

A gate-resistor structure on a semiconductor body, the semiconductor body comprising a plurality of transistor cells and a connecting layer of a first conductivity type or a second conductivity type, the connecting layer comprising a top surface and being configured to be electrically coupled to the plurality of transistor cells, wherein the gate-resistor structure comprises:

• a first semiconductor region of the first conductivity type, extending from the top surface into the connecting layer in a vertical direction;
• a second semiconductor region of the second conductivity type, arranged adjacent to the first semiconductor region, thus forming a pn-junction with the first semiconductor region, the second semiconductor region being arranged below the first semiconductor region in a vertical direction;
• an insulating layer arranged to insulate the first semiconductor region from the surrounding connecting layer;
• and
• a contact layer arranged on the top surface, covering the first semiconductor region to electrically connect the first semiconductor region and additionally covering portions of the top surface beside the first semiconductor region in a horizontal direction.