Insulated gate bipolar transistor with high emitter gate capacitance

An insulated gate bipolar transistor comprising:

• a semiconductor substrate including an active cell region and a termination edge region, wherein the active cell region includes a plurality of emitter regions and gate regions arranged between neighboring emitter regions, each gate region having a gate polysilicon layer and a first insulating layer, wherein each gate polysilicon layer is arranged at a surface of the semiconductor substrate in the gate regions and is separated from the semiconductor substrate by the first insulating layer;
• a first SIPOS layer covered by a second insulating layer, wherein the first SIPOS layer and the covering second insulating layer overlie at least portions of the gate polysilicon layer, the first SIPOS layer being thereby separated from the semiconductor substrate;
• an intermediate third insulating layer, wherein each gate region includes a central area and a peripheral area, and wherein, in the central area, the gate polysilicon layer is in electrical contact with the overlying first SIPOS layer whereas, in the peripheral area, the gate polysilicon layer is electrically separated from the overlying first SIPOS layer by an intermediate third insulating layer;
• and
• an emitter metal layer which overlies the plurality of emitter regions and the gate regions and, at the emitter regions, is in direct contact with the surface of the semiconductor substrate and, at the gate regions, is in direct contact with the second insulating layer.