Counter circuit, analog-to-digital converter, and image sensor including the same and method of correlated double sampling

A method of correlated double sampling, the method comprising:

• counting a first analog signal which represents a reset component in a first counting operation;
• counting a second analog signal which represents a signal component in a second counting operation;
• and
• generating a digital signal which corresponds to a difference between the first analog signal and the second analog signal based on a plurality of results from the first counting operation and the second counting operation, wherein each of the first counting operation and the second counting operation comprises:
• counting a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals during a coarse counting interval based on a first comparison signal, the N-bit counter output signals correspond to each of the first analog signal and the second analog signal;
• and
• counting a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals during a fine counting interval based on the first comparison signal and a second comparison signal, the fine counting interval follows the first coarse counting interval,
• wherein N and M are natural numbers, N is greater than M, and M is greater than or equal to 3.

A method of correlated double sampling for outputting a counter output signal, the method comprising:

• inputting a first counting enable signal during a course counting interval;
• inputting a second counting enable signal during a fine counting interval;
• generating a plurality of upper bits of the counter output signal by counting a first counter clock signal which toggles with a first frequency in response to the first counting enable signal;
• and
• generating a plurality of lower bits of the counter output signal by counting a second counter clock signal which toggles with a second frequency in response to the second counting enable signal,
• wherein the fine counting interval occurs after the course counting interval, and
• wherein the first counting enable signal toggles with a different frequency than the second counting enable signal.