Non-volatile memory with linear hot-electron injection technique and strain gauge using the same
AssigneeBoard of Trustees of Michigan State University
InventorShantanu Chakrabartty
Life of this patent
Estimating the term…
Abstract
A linear hot-electron injection technique is provided for a non-volatile memory arrangement. The non-volatile memory is comprised of: a floating gate transistor; a capacitor with a first terminal electrically coupled to the gate node of the floating gate transistor; a current reference circuit electrically coupled to the source node of the floating gate transistor; and a feedback circuit electrically coupled between the source node of the floating gate transistor and a second terminal of the capacitor. The feedback circuit operates to adjust a voltage at the gate node of the floating gate transistor in accordance with a source-to-drain voltage across the floating gate transistor.
Claims19
1-22. (canceled)
A self-powered static-strain sensor, comprising:
- a piezoelectric member that generates a voltage in response to as mechanical strain;
- and
- a non-volatile memory circuit powered by the voltage received from the piezoelectric member and includes
- a floating gate transistor having a gate node and a source node;
- a capacitor having a first terminal and a second terminal, the first terminal electrically coupled to the gate node of the floating gate transistor;
- a current reference circuit electrically coupled to the source node of the floating gate transistor and operable to source a current therein;
- and
- a feedback circuit electrically coupled between the source node of the floating gate transistor and the second terminal of the capacitor, and operable to adjust a voltage at the gate node of the floating gate transistor in accordance with a source-to-drain voltage across the floating gate transistor.
A self-powered static-strain sensor, comprising:
- a piezoelectric member that generates a voltage in response to as mechanical strain;
- a non-volatile memory arrangement having an array of memory circuits powered by voltage received from the piezoelectric member, each memory circuit includes
- a floating gate transistor having a gate node and a source node;
- a capacitor having a first terminal and a second terminal, the first terminal electrically coupled to the gate node of the floating gate transistor;
- a current reference circuit electrically coupled to the source node of the floating gate transistor and operable to source a current therein;
- a feedback circuit electrically coupled between the source node of the floating gate transistor and the second terminal of the capacitor, and operable to adjust a voltage at the gate node of the floating gate transistor in accordance with a source-to-drain voltage across the floating gate transistor;
- and
- a switch electrically coupled between the second terminal of the capacitor and ground;
- and
- a controller interfaced with each of the switches in the array of memory circuits to control operation thereof.
A self-powered static-strain sensor, comprising:
- a piezoelectric member having a first and second terminal and operable to generate a voltage signal in response to a mechanical strain;
- a first rectifier electrically coupled to the first terminal of the piezoelectric member and operable to extract a positive voltage from the voltage signal;
- a first non-volatile memory circuit powered by the positive voltage received from the first rectifier, the first non-volatile memory includes
- a first floating gate transistor having a gate node and a source node;
- a first capacitor having a first terminal and a second terminal, the first terminal electrically coupled to the gate node of the first floating gate transistor;
- a first current source electrically coupled to the source node of the first floating gate transistor and operable to source an injection current into the first floating gate transistor;
- and
- a first feedback circuit electrically coupled between the source node of the first floating gate transistor and the second terminal of the first capacitor, and operable to adjust a voltage at the gate node of the floating gate transistor in accordance with a source-to-drain voltage across the first floating gate transistor;
- a second rectifier electrically coupled to the second terminal of the piezoelectric member and operable to extract a negative voltage from the voltage signal;
- a second non-volatile memory circuit powered by the negative voltage received from the second rectifier, the second non-volatile memory includes
- a second floating gate transistor having a gate node and a source node;
- a second capacitor having a first terminal and a second terminal, the first terminal electrically coupled to the gate node of the second floating gate transistor;
- a second current source electrically coupled to the source node of the second floating gate transistor and operable to source an injection current into the second floating gate transistor;
- and
- a second feedback circuit electrically coupled between the source node of the second floating gate transistor and the second terminal of the first capacitor, and operable to adjust a voltage at the gate node of the second floating gate transistor in accordance with a source-to-drain voltage across the second floating gate transistor.
Dependencies are inferred from the claim text.