High-efficiency solar photovoltaic cells and modules using thin crystalline semiconductor absorbers

A method for forming a semiconductor solar cell wherein a selective emitter region is formed, comprising:

• depositing dopant precursors with different dopant concentrations;
• structuring said regions by means of laser ablation forming regions with higher dopant precursor concentration and regions with lower dopant precursors;
• and
• driving in said dopant from the predeposited dopant sources using a thermal annealing step.

A back contact crystalline semiconductor solar cell, comprising:

• a crystalline semiconductor substrate, said substrate comprising a light capturing frontside surface and a backside surface for forming emitter and base contacts;
• a first electrically conductive metallization layer having an interdigitated pattern of emitter electrodes and base electrodes on said backside surface of said crystalline substrate, said first electrically conductive interconnect layer having a thickness less than approximately 40 microns;
• a backplane attached to said backside surface of said crystalline substrate, said backplane laminated to said backside surface of said crystalline substrate and comprising a prepeg layer;
• and
• a second electrically conductive metallization layer providing high-conductivity cell interconnects connected to said first electrically conductive interconnect layer via holes in said backplane, said second electrically conductive interconnect layer having an interdigitated pattern of emitter electrodes and base electrodes.

A method for forming a back contact solar cell, comprising:

• forming a porous silicon seed and release layer with at least two different porosities on the surface of a crystalline silicon template;
• depositing an epitaxial semiconductor layer on said porous silicon seed and release layer, said epitaxial silicon layer having a thickness less than 100 microns and an in-situ-doped base region, and said epitaxial silicon layer comprising doped emitter regions and a backside surface for forming emitter and base contacts with said in-situ-doped base regions and said doped emitter region;
• depositing a first layer of electrically conductive metal having an interdigitated pattern of base electrodes and emitter electrodes on said backside surface of said epitaxial silicon layer, said first layer of electrically conductive metal having a thickness less than 2 microns;
• depositing a first layer of electrically conductive metal having an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, said first layer of electrically conductive metal having a thickness approximately less than 40 microns;
• laminating a prepeg backplane to said first layer of electrically conductive metal, said prepeg backplane providing electrical isolation between said first layer of electrically conductive metal and a second layer of electrically conductive metal;
• forming holes in said prepeg backplane according to a laser process, said holes providing access to said first layer of electrically conductive metal;
• and
• applying a second electrically conductive metallization layer on top of this structure, said second electrically conductive metallization layer contacting said first electrically conductive metal layer through said holes.