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US 2015/0014758 A1Published application
Memory cells having a folded digit line architecture
AssigneeMicron Technology, Inc.
InventorShigeki Tomishima
Life of this patent
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Abstract
Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row.
Claims27
A memory device, comprising:
- a plurality of memory cells arranged in a grid pattern comprising a plurality of rows and columns;
- a plurality of column isolation trenches, wherein each of the column isolation trenches is arranged between adjacent columns of the plurality of memory cells, wherein each of the column isolation trenches is linear throughout an entire length of the plurality of columns;
- and
- a plurality of row isolation trenches, wherein each of the row isolation trenches is arranged between adjacent rows of the plurality of memory cells, and wherein each of the plurality of row isolation trenches is non-linear throughout an entire length of the plurality of rows.
1 more element
A memory device, comprising:
- an array of finFETs arranged in a plurality of rows and columns, wherein each of the finFETs comprises a first leg, a second leg, and a shallow trench formed therebetween, and wherein at least one finFET in a row of the array is shifted with respect to at least another finFET in the row, in a direction parallel to the columns.
A memory device, comprising:
- an array of memory cells arranged in a plurality of rows and columns, wherein at least one memory cell in a row of the array is shifted with respect to at least another memory cell in the row, in a direction parallel to the columns;
- a plurality of column isolation trenches, wherein each of the column isolation trenches is arranged between adjacent columns of the array of memory cells, wherein each of the column isolation trenches is linear throughout an entire length of the plurality of columns;
- and
- a plurality of row isolation trenches, wherein each of the row isolation trenches is arranged between adjacent rows of the array of memory cells, and wherein each of the plurality of row isolation trenches is non-linear throughout an entire length of the plurality of rows.
1 more element
Dependencies are inferred from the claim text.