Apparatuses and methods for error correction

An apparatus comprising:

• asynchronous circuitry comprising:
• an input register configured to serially receive a digit stream, the digit stream comprising substrings of a predetermined length of digits;
• and
• a parity circuit in a pipelined architecture configured to determine parity of defined regions of a substring of the digit stream, and to generate indications of parity of the defined regions, wherein the parity circuit is configured to incrementally generate parity information when the pipeline is advanced with new information from the digit stream.

An apparatus comprising:

• a counter circuit configured to update a counter output each time a bit of a bitstream is received by a shift register, the bitstream comprising substrings of a predetermined length of bits, wherein a value of the counter output is associated with how many bits of a selected substring have been received by the shift register, wherein the counter output comprises a plurality of output bits;
• and
• a parity circuit comprising:
• a plurality of parity region circuits of a first type, wherein each of the parity region circuits of a first type comprises a combinatorial logic gate and a first T flip-flop, wherein the combinatorial logic gate is configured to receive a selected output bit of the counter output and the bit of the bitstream as an input and to generate an output that is provided as a trigger input to the first T flip-flip;
• and
• a parity region circuit of a second type comprising a second T flip-flop, wherein the input of the parity region circuit of the second type is configured to receive the bit of the bitstream as an input.