Managing ir drop
AssigneeSTMicroelectronics International N.V.
InventorAjay Kumar Dimri
Life of this patent
Estimating the term…
Abstract
An apparatus has a large block of synchronous logic arranged to include a first partition and a second partition. The first partition is configured to receive a first clock signal during a functional mode and during a test mode. The second partition is configured to receive the first clock signal during the functional mode, and the second partition configured to receive a second clock signal during a test mode. The second clock signal has the same frequency as the first clock signal. The second clock signal has a different phase from the first clock signal.
Claims20
An apparatus, comprising:
- a large block of synchronous logic, the large block of synchronous logic arranged to include at least a first partition and a second partition, the first partition configured to receive a first clock signal during a functional mode and the first partition configured to receive the first clock signal during a test mode, the second partition configured to receive the first clock signal during the functional mode and the second partition configured to receive a second clock signal during a test mode, wherein said second clock signal has a same frequency as said first clock signal and said second clock signal has a different phase from said first clock signal.
A method to test an apparatus, comprising:
- providing a first clock signal to a first partition of a large block of synchronous logic;
- and
- providing a second clock signal to a second partition of the large block of synchronous logic, wherein said second clock signal has a same frequency as said first clock signal and said second clock signal has a different phase from said first clock signal.
An integrated circuit, comprising:
- a large block of synchronous logic, the large block of synchronous logic arranged to include at least a first partition and a second partition, the first partition configured to receive a first clock signal and the second partition configured to receive a second clock signal;
- and
- a switching circuit, the switching circuit configured to receive the first clock signal at a first node, the switching circuit configured to receive a delayed clock signal at a second node, and the switching circuit configured to pass either the first clock signal or the delayed clock signal as the second clock signal from an output node,
Dependencies are inferred from the claim text.