Scheme for Masking Output of Scan Chains in Test Circuit
AssigneeSynopsys, Inc.
InventorsJyotirmoy Saikia, Rohit Kapur
Life of this patent
Estimating the term…
Abstract
A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If the condition is met, a mask that protects the primary fault of the test pattern is generated.
Claims20
A computer implemented method for masking scan chains in a test circuit of an integrated circuit, the method comprising:
- generating, by a computer, a test pattern including a plurality of input values for detecting a primary fault representing a fault for which an initial subset of input values in the test pattern is generated, at least one secondary fault representing a fault detectable by specifying input values other than the initial subset of input values, and at least one tertiary fault representing a fault detectable by the test pattern specified with the input values for the primary and the at least one secondary fault;
- responsive to a condition not being met, generating first mask data configured to mask a first subset of scan chains to increase a total number of detectable primary, secondary, and tertiary faults associated with the test pattern;
- and
- responsive to the condition being met, generating second mask data configured to mask a second subset of scan chains to protect the primary fault associated with the test pattern.
The method of claim 11, further comprising:
- masking a scan chain responsive to a number of undetermined values in the scan chain being greater than a second threshold and responsive to the scan chain not containing a test response corresponding to the primary fault.
A system for masking scan chains in a test circuit of an integrated circuit comprising:
- a test pattern generator, configured to generate a test pattern including a plurality of input values for detecting a primary fault representing a fault for which an initial subset of input values in the test pattern is generated, at least one secondary fault representing a fault detectable by specifying input values other than the initial subset of input values, and at least one tertiary fault representing a fault detectable by the test pattern specified with the input values for the primary and the at least one secondary fault;
- and
- a mask generator configured to:
- generate a first mask data configured to mask a first subset of scan chains to increase a total number of detectable primary, secondary, and tertiary faults associated with the test pattern in response to a condition not being met, and
- generate a second mask data configured to mask a second subset of scan chains to protect a primary fault associated with the test pattern in response to the condition being met.
A non-transitory computer readable medium for masking scan chains in a test circuit of an integrated circuit configured to store instruction, the instructions when executed by a processor cause the processor to:
- generate a test pattern including a plurality of input values for detecting a primary fault representing a fault for which an initial subset of input values in the test pattern is generated, at least one secondary fault representing a fault detectable by specifying input values other than the initial subset of input values, and at least one tertiary faults representing a fault detectable by the test pattern specified with the input values for the primary and the at least one secondary fault;
- responsive to a condition not being met, generate a first mask data configured to mask a first subset of scan chains to increase a total number of detectable primary, secondary, and tertiary faults associated with the test pattern;
- and
- responsive to the condition being met, generate a second data configure to mask a second subset of scan chains to protect a primary fault associated with the test pattern in response to the condition being met.
Dependencies are inferred from the claim text.