Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan Chains
AssigneeMentor Graphics Corporation
InventorsJanusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
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AssigneeMentor Graphics Corporation
InventorsJanusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
Estimating the term…
Aspects of the invention relate to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. Every clock cycle, scan chains configured by a control signal to operate in a shifting-launching mode shift in test stimuli one bit and immediately applies the newly formed test pattern to the circuit-under-test; and scan chains configured by the control signal to operate in a capturing-compacting-shifting mode shift out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data. A large number of scan chains may be configured by the control signal to work in a mission mode. After a predetermined number of clock cycles, a different control signal may be applied to reconfigure and partition the scan chains for applying different test stimuli.
An integrated circuit, comprising:
One or more processor-accessible memories or storage devices storing processor-executable instructions for causing one or more processors to create a design of the integrated circuit, the integrated circuit comprising:
A method, comprising:
Dependencies are inferred from the claim text.