Accessing data stored in a command/address register device
AssigneeIntel Corporation
InventorsKuljit S. Bains, Klaus J. Ruff, George Vergis, Suneeta Sah
Life of this patent
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Abstract
A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.
Claims20
In a memory subsystem, a method comprising:
- logging information about a memory command in a register device coupled to a dynamic random access memory (DRAM) device over an address bus of the memory subsystem, the register device not coupled to a data bus of the memory subsystem;
- detecting a read trigger for the log information in the register device;
- and
- in response to detecting the read trigger, writing the log information to a multipurpose register (MPR) of the DRAM device, the MPR to make the log information accessible to a host processor over the data bus.
An article of manufacture comprising a computer-readable storage medium having content stored thereon, which when executed in a memory subsystem cause the memory subsystem to perform operations including:
- logging information about a memory command in a register device coupled to a dynamic random access memory (DRAM) device over an address bus of the memory subsystem, the register device not coupled to a data bus of the memory subsystem;
- detecting a read trigger for the log information in the register device;
- and
- in response to detecting the read trigger, writing the log information to a multipurpose register (MPR) of the DRAM device, the MPR to make the log information accessible to a host processor over the data bus.
A memory subsystem, comprising:
- a multipurpose register (MPR) of a dynamic random access memory (DRAM) device, the MPR being writeable via an address bus of the memory subsystem and readable via a data bus of the memory subsystem;
- and
- a register device coupled to the MPR on the address bus and not coupled to a data bus of the memory subsystem, to log information about a memory command, and write the log information to the MPR in response to a read trigger received at the register device to make the log information accessible at the MPR,
- wherein a host processor coupled to the memory subsystem is to read the log information from the MPR over the data bus.
Dependencies are inferred from the claim text.