Energy-efficient pipeline circuit templates for high-performance asynchronous circuits
AssigneeCornell University
InventorsRajit Manohar, Basit Riaz Sheikh
Life of this patent
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Abstract
Asynchronous circuits and techniques are described for asynchronous processing without synchronization to a common clock. Two specific energy-efficient pipeline templates for high throughput asynchronous circuits are provided as examples based on single-track handshake protocol. Each pipeline contains multiple stages of logic. The handshake overhead is minimized by eliminating validity and neutrality detection logic gates for all input tokens as well as for all intermediate logic nodes. Both of these templates can pack significant amount of logic within each pipeline block, while still maintaining a fast cycle time.
Claims22
A device for asynchronous processing without synchronization to a common clock, comprising:
- two or more asynchronous circuits that are connected to form an asynchronous processing pipeline, each asynchronous circuit including:
- first input conductive wires that receive and carry a first input signal,
- a first input acknowledgment conductive wire that receives a first input acknowledgment signal from another asynchronous circuit that produces the received first input signal;
- a first asynchronous processing module that processes the first input signal to produce a first output signal;
- a first completion detection processing module that receives the first input acknowledgment signal and the first output signal from the first asynchronous processing module and is operable to produce a first output acknowledgment signal indicating completion of processing of the received first input signal and generation of the first output signal;
- a first output acknowledgment conductive wire that receives the first output acknowledgment signal from the first completion detection processing module and outputs the first output acknowledgment signal;
- and
- first output conductive wires that receive and carry the first output signal generated by the first asynchronous processing module.
A method for asynchronous processing without synchronization to a common clock, comprising:
- connecting asynchronous circuits in series to form an asynchronous processing pipeline to allow one asynchronous circuit to communicate with next adjacent asynchronous circuit to communicate while permitting each asynchronous circuit to perform signal processing, without a common clock;
- operating two adjacently connected asynchronous circuits in the asynchronous processing pipeline to communicate by directing signals from one of the two adjacently connected asynchronous circuits that is upstream relative to the other asynchronous circuit without having an acknowledgment feedback from the downstream asynchronous circuit to the upstream asynchronous circuit;
- operating each asynchronous circuit to encode an input or output signal by using a plurality of conductive wires to carry the input or output signal and by having only a single wire of the plurality of conductive wires asserted at a time;
- and
- operating each asynchronous circuit to use a single conductive wire, which is additional to the conductive wires for carrying output signal from the upstream asynchronous circuit to the downstream asynchronous circuit, to send an acknowledgment signal to the downstream asynchronous circuit.
Dependencies are inferred from the claim text.