Software controlled instruction prefetch buffering

A method to prefetch instructions from memory to a buffer comprising a storage array wherein:

• the said processor having memory fetch latency less than or equal to the processor's CPI;
• the said array comprises multiple storage locations;
• the said array is placed between the memory and the processor;
• the said array has an addition of control words to the user code through compiler or other software;
• the said control words are added to assist the said buffering mechanism to prefetch the next instructions;
• the said control words are inserted in the code where a conditional/unconditional branch, jumps function call/return, or any other instruction that requires additional cycles to compute address and may result in halting the instruction pipeline;
• the said buffer has locations specific to the instructions to be fetched if the conditional branch is taken and the other if the branch is not taken;
• and,
• the said buffer uses a default location to prefetch the next instruction to be executed for unconditional branches, jumps, function call/return, or any other instruction that does not fit into the category of conditional branch.