User-Level Hardware Branch Records
AssigneeAdvanced Micro Devices, Inc.
InventorsJoseph Lee Greathouse, Anton Chernoff
Life of this patent
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Abstract
A processor, a method and a computer-readable medium for recording branch addresses are provided. The processor comprises hardware registers and first and second circuitry. The first circuitry is configured to store a first address associated with a branch instruction in the hardware registers. The first circuitry is further configured to store a second address that indicates where the processor execution is redirected to as a result of the branch instruction in the hardware registers. The second circuitry is configured to, in response to a second instruction, retrieve a value of at least one of the registers. The second instruction can be a user-level instruction.
Claims21
A processor comprising:
- hardware registers;
- first circuitry configured to, in response to a branch instruction:
- store a first address in one of the hardware registers, wherein the first address is associated with the branch instruction;
- and
- second circuitry configured to, in response to a second instruction, retrieve a value of at least one of the hardware registers, wherein the second instruction is a user-level instruction.
A computer-implemented method comprising:
- retrieving a branch instruction;
- storing a first address in one of a plurality of hardware registers, wherein the first address is associated with the branch instruction;
- and
- retrieving, in response to a second instruction, a value of at least one of the registers, wherein the second instruction is a user-level instruction.
A computer-readable storage medium having instructions stored thereon, execution of which by a processor cause the processor to perform operations, the operations comprising:
- executing a branch instruction;
- storing a first address in one of the hardware registers, wherein the first address is associated with the branch instruction;
- and
- retrieving, in response to a second instruction, a value of at least one of the registers, wherein the second instruction is a user-level instruction.
Dependencies are inferred from the claim text.