Processor with inter-execution unit instruction issue

A processor, comprising:

• a processor core, comprising:
• a primary execution unit;
• and
• a secondary execution unit coupled to the primary execution unit;
• wherein the secondary execution unit is configured to provide instructions to the primary execution unit for execution by the primary execution unit in conjunction with execution of a given instruction by the secondary execution unit.

A processor, comprising:

• a processor core, comprising:
• a first execution unit comprising registers and function logic, and configured to execute instructions;
• and
• a second execution unit comprising registers and function logic, and configured to:
• execute instructions;
• and
• provide instructions to the first execution unit for execution in conjunction with an instruction executed by the second execution unit;
• and
• an instruction store configured to store instructions for execution by the first execution unit;
• a merge unit coupled to the first execution unit and the second execution unit, and configured to:
• assign a priority value to each of the instruction store and the second instruction unit, and to insert instructions from the instruction store and the second instruction unit into a stream of instructions to be executed by the first execution unit in accordance with the assigned priorities;
• assert a wait signal to the first execution unit in conjunction with inserting an instruction from the second execution unit into the instruction stream to enable execution of the instruction from the second execution unit by the first execution unit.